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Sr Principal FPGA Verification Engineer

Austin, TX, USA | BAE Systems

  • Industry:
    Airlines/Aviation/Aerospace
  • Position Type:
    Full-Time
  • Functions:
    Engineering
  • Experience:
    10-12 years
Job Description:
53 people have viewed this job

Due to continued growth, BAE Systems has openings for Senior Principal SystemVerilog/UVM FPGA Verification Engineers at locations in Austin, TX, San Diego, CA, Burlington, MA, and Nashua, NH. BAE Systems is one of the world's leading defense contractors and a stable Fortune 500 Company.


In this role, you will lead a team of verification engineers responsible for developing configurable UVM testbenches to simulate and verify complex VHDL FPGA designs that include ADC/DAC interfaces, DSP, and high speed SERDES. You will have the opportunity to drive the SystemVerilog/UVM methodology on a project while working in a fast-paced, dynamic environment. You and your team will be expected to develop reusable Universal Verification Components (UVCs) including agents, monitors, scoreboards, etc. The team will also develop test cases, collect/analyze coverage, and run interactive and regression simulations. There are opportunities to create new verification environments, as well as to improve on leveraged environments.


As an experienced Verification Engineer, you will have the opportunity to mentor junior engineers on SystemVerilog, UVM, and the Verification Process in a fast growing organization. You will also have the opportunity to be mentored by other engineers to develop your skills in the ever-changing Electronic Warfare domain. Working with systems engineers, FPGA designers, and other verification engineers, you will come to understand BAE products from the system level design down to the individual FPGAs.


Our flexible work environment provides a work life balance that affords you the opportunity to change the world while maintaining your personal life. We put our customers first – exemplified by our mission: “We Protect Those Who Protect Us®”.


Required Skills and Education

- Experience in SystemVerilog/UVM or OVM

- Experience in developing constrained random, self checking testbenches

- Experience with FPGA design and verification tools (Mentor Questa)

- Experience in creating Universal Verification Components (agents, monitors, scoreboards)

- The ability to obtain a Secret level security clearance


Preferred Skills and Education

- Bachelor's Degree and 10 years relevant work experience (or equivalent)

- Experience as a DV team lead on one or more successful projects

- Digital Signal Processing experience

- Matlab/Simulink

- Perl/Python

- VHDL Design experience

- Hold an active Secret clearance


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