Tech Lead, ASIC Design Verification
San Jose, CA, USA | Cisco
Job Description:98 people have viewed this job
The Datacenter Networking Business Unit is looking for an experienced Asic Verification Engineer to engage in new development of our UCS/Nexus 9K family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.
Who You'll Work With
Come join us and take part in shaping Cisco’s revolutionary solutions for datacenters by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!
Who You Are
You collaborate closely with verification engineers, designers, hardware & cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up.
Architect block, cluster and top level DV environment infrastructure
Maintaining existing DV environments and enhancing them
Ensuring complete verification coverage through implementation and review of code and functional coverage
Working closely with designers
Be responsible for ASIC bringup
Bachelor’s or Master’s degree in EE .
10+ years of ASIC Verification experience.
Knowledge and Skills:
You are proficient in asic verification using UVM/System Verilog.
You are proficient in verifying complex blocks, clusters and top level for SoC
You can build testbenches from scratch
You are familiar with Perl and/or Python scripting
You have the ability to collaborate with cross-functional teams, and possess the drive to learn and grow
Formal verification (iev/vc formal) knowledge is a plus
Experience of verification using C++ is a plus